Very urgent openings for Physical Design Engineer with a well known Semiconductor MNC
Position: Physical Design Engineer/Lead
Location:
Experience: 4-7 Years
Job Description:
He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as
Skills Required:
Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure
Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
Expertise in scripting languages such as PERL, TCL
Strong Physical Verification skill set.
Static Timing Analysis in Primetime or Primetime-SI
If you are interested mail your updated CV to ashwinikn@roljobs.com with following details
Kindly refer people in your network who may be interested
Ashwini
HR Recruiter-Social Media Recruitment Team
Roland & Associates-Leaders in Social Media Recruitment
Tel: 080-42821618
Email: ashwinikn@roljobs.com
Linkedin:http://in.linkedin.com/pub/ashwini-ashwinikn-roljobs-com/39/a92/774
Website:www.roljobs.com,www.roljob.net,www.aerojobs.net
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