Location:  
 
Experience:3-7 years
Job  Description:
He/She should be able to do top-level floor planning, PG  Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis,  timing optimization, SI aware routing, timing analysis/closure and ECO tasks  (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical  vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or  lower node designs with adv low power techniques such as  
Skills Required:   
-    Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure
 -    Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
 -    Expertise in scripting languages such as PERL, TCL
 -    Strong Physical Verification skill set.
 -    Static Timing Analysis in Primetime or Primetime-SI
 
If you are interested mail your updated CV to ashwinikn@roljobs.com
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Regards
Ashwini
HR Recruiter 
Roland & Associates-Leaders in Social Media  Recruitment


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