Onsite opportunity for Physical Design Engineer

Dear Professionals 

 

          Hiring Physical Design Engineers for a service based semiconductor MNC 

 

Location: USA

 

Experience:3-7 years

 

Job Description:

He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias

 

Skills Required:  

1. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure
2. Extensive experience and detailed knowledge in Aprisa Tools.
3. Expertise in scripting languages such as PERL, TCL
4. Strong Physical Verification skill set.
5. Static Timing Analysis in Primetime or Primetime-SI 

 

If you are interested mail your updated CV to ashwinikn@roljobs.com

 

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Regards
Ashwini
HR Recruiter-Social Media Recruitment Team
Roland & Associates-Leaders in Social Media Recruitment
Tel: 080-42821613
Email: ashwinikn@roljobs.com
Linkedin:http://in.linkedin.com/pub/ashwini-ashwinikn-roljobs-com/39/a92/774

Website:www.roljobs.com